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Publication

Title:Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations
Authors:L. Ansari, B. Feldman, G. Fagas, J.-P. Colinge and J.C. Greer, 2012
Abstract: Previously, we reported current–voltage characteristics of silicon nanowire junctionless transistors with a 3 nm gate length and a 1 nm wire diameter as calculated within a Density Functional Theory (DFT) framework. Our results reveal that a 3 nm gate length can provide good electrostatic control over the channel. In this work, sensitivity to dopant position within the nanowire cross section on the band structure is explored. Our calculation of the current–voltage characteristics is extended here by considering the role of charge self-consistency on the charge carrier transport, and in particular the subthreshold slope in these nanowire transistors is examined. Even at such small length scales, the self-consistent calculations indicate that subthreshold slopes of 74 and 80 mV/dec can be obtained for p-channel and n-channel devices, respectively.
ICHEC Project:First Principles Simulation of Junction-less Carbon Nanotube Field Effect Transistors (CNT-FETs)
Publication:Solid-State Electronics Volume 71, May 2012, Pages 58–62
URL: http://dx.doi.org/10.1016/j.sse.2011.10.021
Keywords: Ab initio calculations, Electronic transport, Elemental semiconductors, Nanowire, NEGF, Silicon, Transistors
Status: Published

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