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Publication

Title:Simulation of junctionless Si nanowire transistors with 3 nm gate length
Authors:Lida Ansari, Baruch Feldman, Giorgos Fagas, Jean-Pierre Colinge, and James C. Greer, 2010
Abstract: Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼ 1 nm wire diameter and ∼ 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.
ICHEC Project:First Principles Simulation of Junction-less Carbon Nanotube Field Effect Transistors (CNT-FETs)
Publication:Applied Physics Letters / Volume 97 / Issue 6 / ELECTRONIC TRANSPORT AND SEMICONDUCTORS (2010)
URL: http://link.aip.org/link/doi/10.1063/1.3478012
Keywords: ab initio calculations, elemental semiconductors, nanowires, silicon, transistors
Status: Published

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