2014

Project Start Date

01st Dec 2014

Performance Engineering

xilinx

Working closely with researchers at the company’s EMEA headquarters in Dublin, ICHEC’s team of HPC applications experts are enabling and optimising several important HPC and data processing algorithms on Xilinx FPGAs with focus on both performance and energy efficiency. The work carried out performance engineering of several applications relevant to data centre middleware and machine learning using Xilinx SDAccel™ development environment for OpenCL, C and C++ application and on creating FPGA optimised libraries using Vivado HLS technology.

Our work as been inspired by recent research investigation on dataflow architecture for key-value stores that can sustain a consistent 10Gbps line-rate and which bring significant latency benefits through tight coupling of network interface, memory and compute resources. At the heart of a key-value store architecture, such as memcached, is a harsh table, which in essence determines the memory address of a value as a function of an incoming key. This is achieved by first applying the chosen harsh function to the contents of a key to produce as address in the table. From this location, a pointer to the address within the value storage area can be retrieved.

ICHEC is a proud member of the Xilinx Alliance Programme 2014- 2016